1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory.
2. Background Art
To improve the performance of SSDs, Smart Phones, Tablet PCs or the like, there is a strong demand for improving the performance of the systems incorporating NAND flash memories.
Recent NAND-type flash memories incorporate a fast toggle DDR interface to improve the read-out throughput and can transfer data at high rates of 133 Mbps to 400 Mbps. The power supply voltage “VccQ” for I/O is typically 1.8 V in order to reduce the power and current consumptions in data transfer.
As the size of memory cells is scaled down, the interference between adjacent cells, the program noise or other noise, the RC time constant of the bit lines and the word lines and the like are deteriorating. In the state of art, it is barely possible to maintain the writing throughput of the previous-generation NAND-type flash memory.
To improve the writing throughput, the size of the page written at one time has been increased from 2 KB to 4 KB, to 8 KB, to 16 KB, 32 KB and then to 64 KB. However, further increasing the page size is impracticable because the chip size and the current consumption substantially increase.
To improve the writing performance of the memory system, there is a solution of activating a plurality of chips of NAND-type flash memories at the same time. However, since a plurality of chips operate at the same time, the power and current consumptions increase accordingly. The number of chips that operate at the same time is limited so that the system's capability of supplying power or current is not exceeded, or the temperature of the chips, which consume power and generate heat, does not exceed the guaranteed temperature. To improve the performance, the number of chips that operate at the same time has to be further increased, and to this end, there is a strong demand for reducing the power consumption and current consumption of the NAND-type flash memories.
One solution to reduce the power consumption is to reduce the power supply voltage “Vcc” to 1.8 V. In fact, products using the power supply voltage “Vcc” of 1.8 V have already been commercialized in applications where low power consumption is particularly demanded.
The NAND-type flash memory requires approximately 5 to 25 V for writing and approximately 5 to 10 V for reading, and these voltages have to be generated by a charge pump circuit in the chip.
Unfortunately, charge pump circuits that generate the high voltages from the power supply voltage “Vcc” of 1.8 V has a larger area, requires a larger chip size and consumes a higher current than charge pump circuits that generate the high voltages from the power supply voltage “Vcc” of 3.3 V.